A sense amplifier-based monotonic register (“SA-based register”) is a register element (also known as a latch element) that has a first stage that is a sense amplifier. “Monotonic” refers to a data transition characteristic of the true and complement output signals of the latch. The true and complement output signals are “monotonic” when exactly one of these output signals transitions, and transitions only once, during a given clock period.
FIG. 4 shows an example of a conventional SA-based register 400. This SA-based register has one drawback, stemming from the fact that its output signals Q and Q develop while the sense amplifier is clocked. During that time, as clock signal CLK switches on NMOS transistor NL and switches off PMOS transistors P3 and P4, one or both of the voltages of output signals QT and QC may drop when the node becomes high impedance and a capacitive voltage divider is formed between the capacitive load the node is driving and the drain/channel capacitance one of cross-coupled NMOS transistors N1 and N2, as the transistor turns on. As these output signals QT and QC are also regenerative feedback signals that would amplify any small voltage difference between the gate terminals of NMOS transistors N3 and N4 immediately, leading to a metastable condition. Such a metastable condition may result in erroneous operation (i.e., an incorrect data value being captured at the output terminals), particularly when a device mismatch condition exists, as discussed in further detail below. The correct operation of the SA-based register is thus sensitive to the slew rate of the clock signal. To minimize the chance of a metastable condition from developing, additional transistors are often added to avoid a consequential differential signal from developing at sensitive internal nodes during a clock signal transition.
SA-based registers are sensitive to device mismatches. Inevitable manufacturing variations in channel lengths or widths of transistors or other device characteristics (e.g., threshold voltages) may result in mismatch or imbalance in transistor pairs that are required to be matching or balanced for correct operation. In addition, manufacturing imperfection may result in stress-induced enhanced mobility effects in the transistors that are known to be sources of erroneous operations in SA-based registers. Also, asymmetric effects (e.g., asymmetrical loads at the terminals of a differential output terminal) may result in poor rejection of power supply noise. The SA-registers are particularly vulnerable to power supply noise during activation. The initial conditions at internal nodes and leakage from such internal nodes may also lead to erroneous operations in an SA-based register.